agilent HMMC-3028 dcC 12 ghz high efficiency gaas hbt mmic divide-by-8 prescaler data sheet description the HMMC-3028 gaas hbt mmic prescaler offers dc to 12 ghz frequency translation for use in communications and ew systems incorporating high- frequency pll oscillator circuits and signal-path down conversion applications. the prescaler provides a large input power sensitivity window and low phase noise. in addition to the features listed above the device offers an input disable contact pad to eliminate any self- oscillation condition. features ? wide frequency range: 0.2 12 ghz ? high input power sensitivity: on-chip pre- and post-amps -20 to +10 dbm (1 8 ghz) -15 to +10 dbm (8 10 ghz) -10 to +5 dbm (10 12 ghz) ? dual mode p out : (chip form) 0 dbm (0.5 v p-p ) @ 44 ma -6.0 dbm (0.25 v p-p ) @ 34 ma ? low phase noise: -153 dbc/hz @ 100 khz offset ? (+) or (-) single supply bias operation ? wide bias supply range: 4.5 to 6.5 volt operating range ? differental i/o with on-chip 50 ? matching absolute maximum ratings [1] (@ t a = 25 c, unless otherwise indicated) symbol parameters/conditions units min. max. v cc bias supply voltage v +7 v ee bias supply voltage v -7 [v cc -v ee ] bias supply delta v +7 v disable pre-amp disable voltage v v ee v cc v logic logic threshold voltage v v cc 1.5 v cc 1.2 p in (cw) cw rf input power dbm +10 v rfin dc input voltage (@ rf in or rf in ports) v v cc 0.5 t bs [2] backside operating temperature c -40 +85 t stg storage temperature c -65 +165 t max max. assembly temp. (60 seconds max.) c 310 notes: 1. operation in excess of any parameter limit (except t bs ) may result in permanent damage to this device. 2. mttf >1 x10 6 hours @ t bs 85 c. operation in excess of maximum operating temperature (t bs ) will degrade mttf. chip size: 1330 x 440 m (52.4 x 17.3 mils) chip size tolerance: 10 m ( 0.4 mils) chip thickness: 127 15 m (5.0 0.6 mils) pad dimensions: 70 x 70 m (2.8 x 2.8 mils)
2 HMMC-3028 dc specifications/physical properties (t a = 25 c, v cc - v ee = 5.0 volts, unless otherwise indicated) symbol parameters and test conditions units min. typ. max. v cc - v ee operating bias supply difference [1] v 4.5 5.0 6.5 |i cc | or |i ee | bias supply current ( high output power configuration [2] : v pwrsel = v ee )ma374451 bias supply current ( low output power configuration: v pwrsel = open) ma 29 34 39 v rfin(q) quiescent dc voltage appearing at all rf ports vv cc v rfout(q) v logic nominal ecl logic level vv cc - 1.45 v cc - 1.32 v cc - 1.25 (v logic contact self-bias voltage, generated on-chip) notes: 1. prescaler will operate over full specified supply voltage range. v cc or v ee not to exceed limits specified in absolute maximum ratings section. 2. high output power configuration: p out = 0 dbm (v out = 0.5 v p-p ), low output power configuration: p out = -6.0 dbm (v out = 0.25 v p-p ) rf specifications (t a = 25 c, z 0 = 50 ? , v cc - v ee = 5.0 volts) symbol parameters and test conditions units min. typ. max. in(max) maximum input frequency of operation ghz 12 14 in(min) minimum input frequency of operation [1] ghz 0.2 0.5 (p in = -10 dbm) self-osc. output self-oscillation frequency [2] ghz 1.7 @ dc, (square-wave input) dbm -15 >-25 +10 @ in = 500 mhz, (sine-wave input) dbm -15 >-20 +10 p in in = 1 to 8 ghz dbm -15 >-20 +10 in = 8 to 10 ghz dbm -10 >-15 +5 in = 10 to 12 ghz dbm -5 >-10 +1 rl small-signal input/output return loss db 15 (@ in < 12 ghz) s 12 small-signal reverse isolation db 30 (@ in <12 ghz) ? n ssb phase noise (@ p in = 0 dbm, 100 khz offset dbc/hz -153 from a out = 1.2 ghz carrier) jitter input signal time variation @ zero-crossing ps 1 ( in = 10 ghz, p in = -10 dbm) r or f output edge speed (10% to 90% rise/fall time) ps 70 notes: 1. for sine-wave input signal. prescaler will operate down to d.c. for square-wave input signal. minimum divide frequency limite d by input slew-rate. 2. prescaler may exhibit this output signal under bias in the absence of an rf input signal. this condition may be eliminated by use of the pre-amp disable (v disable ) feature, or the differental input de-biasing technique.
3 v cc input preamplifier stage rf in 50 ? 50 ? rf in v ee v cc v ee v pwrsel 18/36 ma post amplifier stage 50 ? 50 ? rfout rfout v disable divide cell 8 figure 1. HMMC-3028 simplified schematic. HMMC-3028 rf specifications, continued high output power operating mode [1] (t a = 25 c, z o = 50 ? , v cc - v ee = 5.0v) symbol parameters and test conditions units min. typ. max. @ ? out < 1 ghz dbm -2.0 0 p out @ ? out = 1.25 ghz dbm -2.0 0 @ ? out = 1.5 ghz dbm -2.25 -0.25 @ ? out < 1 ghz volts 0.39 0.5 |v out(p-p) |@ ? out = 1.25 ghz volts 0.39 0.5 @ ? out = 1.5 ghz volts 0.38 0.48 ? out power level appearing at rf in or rf in dbm -61 p spitback (@ ? in = 10 ghz, unused rf out or rf out unterminated ) ? out power level appearing at rf in or rf in dbm -81 (@ ? in = 10 ghz, both rf out & rf out terminated ) p feedthru power level of ? in appearing at rf out or rf out dbc -30 (@ ? in = 12 ghz, p in = 0 dbm, referred to p in ( ? in )) h 2 second harmonic distortion output level dbc -30 (@ ? out = 1.5 ghz, referred to p out ( ? out )) low output power operating mode [2] @ ? out < 1 ghz dbm -8.0 -6.0 p out @ ? out = 1.25 ghz dbm -8.0 -6.0 @ ? out = 1.5 ghz dbm -8.25 -6.25 @ ? out < 1 ghz volts 0.20 0.25 |v out(p-p) |@ ? out = 1.25 ghz volts 0.20 0.25 @ ? out = 1.5 ghz volts 0.19 0.24 ? out power level appearing at rf in or rf in dbm -71 p spitback (@ ? in = 10 ghz, unused rf out or rf out unterminated ) ? out power level appearing at rf in or rf in dbm -91 (@ ? in = 10 ghz, both rf out & rf out terminated ) p feedthru power level of ? in appearing at rf out or rf out dbc -30 (@ ? in = 12 ghz, p in = 0 dbm, referred to p in ( ? in )) h 2 second harmonic distortion output level dbc -35 (@ ? out = 1.5 ghz, referred to p out ( ? out )) notes: 1. v pwrsel = v ee . 2. v pwrsel = open circuit.
4 applications the HMMC-3028 is designed for use in high frequency communi- cations, microwave instrumenta- tion, and ew radar systems where low phase-noise pll control circuitry or broad-band frequency translation is required. operation the device is designed to operate when driven with either a single- ended or differential sinusoidal input signal over a 200 mhz to 12 ghz bandwidth. below 200 mhz the prescaler input is slew-rate limited, requiring fast rising and falling edge speeds to properly divide. the device will operate at frequencies down to dc when driven with a square-wave. the device may be biased from either a single positive or single negative supply bias. the back- side of the device is not dc connected to any dc bias point on the device. for positive supply operation v cc is nominally biased at any voltage in the +4.5 to +6.5 volt range with v ee (or v ee & v pwrsel ) grounded. for negative bias operation v cc is typically grounded and a negative voltage between -4.5 to -6.5 volts is applied to v ee (or v ee & v pwrsel ). several features are designed into this prescaler: 1) dual-output power feature bonding both v ee and v pwrsel pads to either ground (positive bias mode) or the negative supply (negative bias mode), will deliver ~ 0 dbm [0.5v p-p ] at the rf output port while drawing ~ 40 ma supply current. eliminat- ing the v pwrsel connection results in reduced output power and voltage swing, -6.0 dbm [0.25v p-p ] but at a reduced current draw of ~ 30 ma resulting in less over-all power dissipation. (note: v ee must always be bonded and v pwrsel must never be biased to any potential other than v ee or open-circuited.) 2) v logic ecl contact pad under normal conditions no connection or external bias is required to this pad and it is self- biased to the on-chip ecl logic threshold voltage (v cc C1.35 v). the user can provide an external bias to this pad (1.5 to 1.2 volts less than v cc ) to force the prescaler to operate at a system generated logic threshold voltage. 3) input disable feature if an rf signal with sufficient signal to noise ratio is present at the rf input, the prescaler will operate and provide a divided output equal to the input fre- quency divided by the divide modulus. under certain ideal conditions where the input is well matched at the right input frequency, the device may self- oscillate, especially under small signal input powers or with only noise present at the input. this self-oscillation will produce a undesired output signal also known as a false trigger. by applying an external bias to the input disable contact pad (more positive than v cc C1.35v), the input preamplifier stage is locked into either logic high or logic low preventing frequency division and any self-oscillation frequency which may be present. 4) input dc offset another method used to prevent false triggers or self-oscillation conditions is to apply a 20 to 100 mv dc offset voltage be- tween the rf in and rf in ports. this prevents noise or spurious low level signals from triggering the divider. adding a 10 k ? resistor between the unused rf input to a contact point at the v ee potential will result in an offset of 25mv between the rf inputs. note however, that the input sensitiv- ity will be reduced slightly due to the presence of this offset. assembly techniques figure 3 shows the chip assembly diagram for single-ended i/o operation through 12 ghz for either positive or negative bias supply operation. in either case the supply contact to the chip must be capacitively bypassed to provide good input sensitivity and low input power feed- through. independent of the bias applied to the device, the back- side of the chip should always be connected to both a good rf ground plane and a good thermal heat sinking region on the mounting surface. all rf ports are dc connected on-chip to the v cc contact through on-chip 50 ? resistors. under any bias conditions where v cc is not dc grounded, the rf ports should be ac coupled via series capacitors mounted on the thin-film substrate at each rf port. only under bias conditions where v cc is dc grounded (as is typical for negative bias supply operation) may the rf ports be direct coupled to adjacent cir- cuitry or in some cases, such as level shifting to subsequent stag- es. in the latter case the device backside may be floated and bias applied as the difference between v cc and v ee . all bonds between the device and this bypass capacitor should be as short as possible to limit the inductance. for operation at frequencies below 1 ghz, a large value capacitor must be added to provide proper rf bypassing. due to on-chip 50 ? matching resistors at all four rf ports, no external termination is required on any unused rf port. however,
5 figure 2. pad locations and chip dimensions. 0 440 0 rfin 220 70 370 70 650 800 950 1090 1260 350 230 900 260 500 1330 rfin v cc v ccbypass no connection v pwrsel v logic v disable v ee v cc v cc rfout rfout v cc notes: ? all dimensions in microns. ? all pad dim: 70 x 70 m (except where noted) ? tolerances: 10 m ? chip thickness: 127 15 m improved spitback perfor- mance ( ~ 20 db) and input sensi- tivity can be achieved by termi- nating the unused rfout port to v cc through 50 ? (positive supply) or to ground via a 50 ? termination (negative supply operation). optional dc operating values/logic levels (t a = 25 c) function symbol conditions min. typical max. (volts/ma) (volts/ma) (volts/ma) logic threshold [1] v logic v cc 1.5 v cc 1.35 v cc 1.2 v disable(high) [disable] v logic + 0.25 v logic v cc input disable v disable(low) [enable] v ee v logic v logic 0.25 i disable v d > v ee + 3 (v disable v ee 3)/500 (v disable v ee 3)/500 (v disable v ee 3)/500 v d < v ee + 3000 note: 1. acceptable voltage range when applied from external source. gaas mmics are esd sensitive. esd preventive measures must be employed in all aspects of storage, handling, and assembly. mmic esd precautions, handling considerations, die attach and bonding methods are critical factors in successful gaas mmic performance and reliability. agilent application note #54, gaas mmic esd, die attach and bonding guidelines pro- vides basic information on these subjects.
6 to +4.5v to +6.5v v cc supply (bypassed via 1 f capacitor) >300 pf v cc bypass capacitor v ee bond required (gnd) positive supply 3 mil nominal gap (@ device input) ac coupling capacitor(s) ac coupling capacitor (note: must be large enough to pass lowest frequency output signal) rfin rfout rfout rfin optional differential output optional differential input optional 50 ? termination to v cc or gnd if ac coupling cap is employed optional v pwrsel pad connection: w/pad bonded to ground: high p out assembly (0 dbm [0.5 v p-p ] @ i cc = 44 ma) w/pad not bonded to ground: low p out assembly (-6.0 dbm [0.25 v p-p ] @ i cc = 34 ma) to -4.5v to -6.5v v ee supply (bypassed via 1 f capacitor) >300 pf v ee bypass capacitor v ee bond required negative supply 3 mil nominal gap (@ device input) rfin rfout rfout rfin optional differential output optional differential input optional 50 ? termination optional v pwrsel pad connection: w/pad bonded to v ee : high p out assembly (0 dbm [0.5 v p-p ] @ i cc = 44 ma) w/pad not bonded to v ee : low p out assembly (-6.0 dbm [0.25 v p-p ] @ i cc = 34 ma) v cc (bypass) connection to rf ground-plane required) figure 3. assembly diagrams.
7 HMMC-3028 supplemental data 0 2 4 input frequency, ? in (ghz) v cc Cv ee = +5 v, t a = 25 c figure 4. typical input sensitivity window. 20 10 0 -10 -20 -30 -40 input power, p in (dbm) 12 8 610 16 14 figure 5. typical supply current & v logic vs. supply voltage. 50 45 40 35 30 25 20 15 10 5 0 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 i supply (ma) v logic C v cc (v) 01 2 5 34 78 69 v cc Cv ee (v) t a = 25 c high power mode low power mode figure 7. typical output power vs. output frequency, ? out (ghz) . 2 0 -2 -4 -6 p out (@ p in = 0 dbm) (dbm) 0 0.5 1 2.5 1.5 2 output frequency (ghz) high power mode low power mode v cc Cv ee = +5 v, t a = 25 c 024 input frequency, ? in (ghz) v cc Cv ee = +5 v, p in = 0 dbm, t a = 25 c figure 8. typical spitback power. p(? out ) appearing at rf input port. -50 -60 -70 -80 -90 -100 -110 -120 p spitback (dbm) 12 8 610 16182022 14 unterminated rfout port both rfout ports terminated -110 -115 -120 -125 -130 -135 -140 -145 -150 -155 -160 100 1k 10k 100k 1m 10m offset from carrier (hz) ssb phase noise (dbc/hz) p in = 0 dbm, f carrier = 1.2 ghz figure 6. typical phase noise performance.
this data sheet contains a variety of typical and guaranteed performance data. the information supplied should not be interpreted as a complete list of circuit specifications. in this data sheet the term typical refers to the 50th percentile performance. for additional information contact your local agilent technologies sales representative. www.agilent.com/semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (408) 654-8675 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6271 2451 india, australia, new zealand: (+65) 6271 2394 japan: (+81 3) 3335-8152(domestic/international), or 0120-61-1280(domestic only) korea: (+65) 6271 2194 malaysia, singapore: (+65) 6271 2054 taiwan: (+65) 6271 2654 data subject to change. copyright ? 2002 agilent technologies, inc. obsoletes 5968-4527e may 22, 2002 5988-3191en
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